The present invention relates to a semiconductor device, and more particularly, the present invention relates to a semiconductor device having a high-voltage transistor.
A semiconductor device may include a memory cell array including a plurality of memory cells configured to store data and a plurality of peripheral circuits configured to program or erase data into or from the memory cells or read out data stored in the memory cells.
The peripheral circuits may include a plurality of page buffers coupled to the memory cell array through bit lines. The page buffers may provide a program permission voltage or a program prohibition voltage through the bit lines in a program operation and receive states of cells through the bit lines in a read operation.
Meanwhile, interference may occur between adjacent bit lines as a degree of integration of a semiconductor device increases. Thus, in order to prevent the interference, the bit lines are classified into even-numbered bit lines and odd-numbered bit lines. The even-numbered bit lines may be called even bit lines, and the odd-numbered bit lines may be called odd bit lines. Since each of the page buffers is coupled to a bit line pair including an even bit line and an odd bit line, each of the page buffers may include a bit line selection circuit configured to select the even bit line or and the odd bit line of the bit line pair.
FIG. 1 illustrates a layout diagram of a conventional semiconductor device.
Referring to FIG. 1, a page buffer of the semiconductor device may include a bit line selection circuit configured to select an even bit line BLe or an odd bit line BLo in a bit line pair. The bit line selection circuit may include a bit line precharge circuit configured to precharge the even bit line BLe or the odd bit line BLo and a selection circuit configured to select the even bit line BLe or the odd bit line BLo. A portion of the selection circuit is illustrated in FIG. 1.
The selection circuit may include a plurality of transistors TR each of which is configured to select an even or odd bit line in a bit line pair. The transistor TR may be formed in an active region AT of a semiconductor substrate. As the numbers of even and odd bit lines BLe and BLo increase, when all the transistors TR are included in the active region AT disposed on a single line, the length of the selection circuit may significantly increase. Accordingly, selection circuits may be divided into groups, e.g., selection circuit blocks, and respective selection circuit blocks may be disposed apart from one another in a first direction. Each of the selection circuit blocks may include a plurality of selection circuits spaced apart from one another in a second direction perpendicular to the first direction. Each of the selection circuits may include a plurality of contact plugs and a plurality of transistors formed in the active region AT of the semiconductor substrate. Specifically, each of the selection circuits may include a first contact plug, a first gate line, a second contact plug, a second gate line, and a third contact plug disposed sequentially in the first direction. In the same selection circuit block, the first and second gate lines may be disposed across all the active regions AT. Even bit lines BLe may be coupled to the first contact plug, and odd bit lines BLo may be coupled to the third contact plug. Space between the respective active regions AT may be defined as an isolation region IS, which may be filled with an insulating material.
In particular, since a group of even bit lines BLe and a group of odd bit lines BLo are alternately arranged, the even bit lines BLe and the odd bit lines BLo may face each other in adjacent selection circuit regions. For example, when a first group of even bit lines BLe and a first group of odd bit lines BLo are arranged in the first direction in a first selection circuit region, a second group of even bit lines BLe and a second group of odd bit lines BLo may be arranged in the first direction even in a second selection circuit region disposed adjacent to the first selection circuit region in the first direction. Accordingly, the first group of odd bit lines BLo disposed in the first selection circuit region may be disposed opposite to the second group of even bit lines BLe disposed in the second selection circuit region. As described above, when different groups of bit lines are arranged opposite to each other, depletion may occur in the semiconductor substrate disposed under the isolation region IS. To prevent the depletion from occurring, a field stop ion implantation region FS may be formed by performing an ion implantation process on a portion of the semiconductor substrate disposed under the isolation region IS. This configuration will be described in detail with reference to the accompanying drawings.
FIG. 2 is a cross-sectional view taken along a line A-A′ in FIG. 1.
Referring to FIG. 2, an isolation region IS is formed to define active regions AT in a semiconductor substrate 10 and filled with an insulating material 14. Gate lines of transistors TR are formed on the active region AT in the semiconductor substrate 10, and junction regions 12 are formed in the semiconductor substrate 10 adjacent to both ends of each of the gate lines. Thus, the transistors TR including the gate lines and the junction regions 12 are formed. After that, an interlayer insulating layer 17 is formed to cover a resultant structure including the transistors TR, and contact plugs CP are formed on the junction regions 12 to penetrate the interlayer insulating layer 17. Each of bit lines no and BLe is formed over the interlayer insulating layer 17 to be coupled to each of the contact plugs CP.
When high-voltage transistors are formed in a selection circuit region and different voltages are applied to junction regions 12 formed in different active regions AT, depletion may occur in a region between the junction regions 12 in the different active regions AT. To prevent the occurrence of the depletion, an ion implantation process may be performed onto a portion of the semiconductor substrate 10 disposed under the isolation region IS, thereby forming a field stop ion implantation region FS. The field stop ion implantation region FS may be formed by implanting impurities having a different type from that of the junction region 12 formed in the active region AT. Accordingly, if a distance between the field stop ion implantation region FS and the junction region 12 is excessively reduced, a breakdown (BD) voltage may be lowered. To prevent this phenomenon from occurring, a minimum distance between the field stop ion implantation region FS and the junction region 12 should be secured. As a result, an area occupied by a semiconductor device may increase depending on a width W of the field stop ion implantation region FS and the minimum distance between the field stop ion implantation region FS and the junction region 12.